Sponsored by The National Science Foundation


Click this link for the report of this workshop.


The International Technology Roadmap for Semiconductors (ITRS) projects that device scaling will continue well into the sub-nanometer regime, which in turn will provide opportunities to integrate an exponentially increasing number of cores within a single chip. This many-core approach is projected to be the path by which the industry will meet the growing computing demands of scientific, commercial, and consumer workloads. This shift to an ever-increasing number of cores – within a single socket in consumer devices and across multiple sockets in servers – has brought interconnects to the forefront of the challenges facing the computing industry.

The computing capabilities of many-core systems can be harnessed only if the underlying on-chip and chip-to-chip communication fabrics can perform at an acceptable level of power performance efficiency. Thus, the design and implementation of low latency, high bandwidth, and power efficient on-chip and chip-to-chip interconnection networks has become one of the most critical challenges to achieving the performance potential of future many-core systems, and evidence suggests that alternatives to conventional metal interconnects will be needed to meet these demands. While several such promising alternatives have been identified, research in these areas has been largely limited in scope to specific areas of the computing stack, and little progress has been made across problem sub-domains. Thus, there is a dire need for holistic research efforts spanning the stack from physics to systems, and that produce prototypes and development tools that are of much greater sophistication than exist today in order to enable commercial adoption.

While interconnection networks (mostly macro-networks) have been a focus of study for several decades, research in chip-to-chip and on-chip networks has surged in recent years, primarily due to the emergence of multicore architectures and the need for higher bandwidth chip-to-chip interfaces. On-chip and chip-to-chip networks have different cost-performance constraints than rack-level, board-to-board interconnects, that impact power consumption, area, and performance. While metal on-chip and chip-to-chip networks can in theory provide sufficient bandwidth to support multi-socket many-core systems, the various on-chip and chip-to-chip communication fabrics are fast consuming a major portion of the system power budget, leaving insufficient power headroom for cores, memory, and storage. This is a major bottleneck that needs to be urgently addressed to prevent future systems from stagnating in terms of performance.

Recent research has shown that emerging technologies, such as nanophotonics, have the potential to reduce network power consumption by an order of magnitude at the same performance level as conventional metal interconnects. However, each of these emerging technologies is untested for on-chip communication (and to some degree chip-to-chip) and brings a host of challenges. Nanophotonics has already shown to have several advantages suitable for on-chip communication: distance-independent bit-rate, lower performance-per-Watt, reduced area overhead, and many others. However, bringing optics into the chip has its own challenges such as coupling signals, multiplexing multiple wavelengths, device losses, and thermal stability. Another formidable barrier to the adoption of these technologies is that research advances have been piecemeal in nature and there is a lack of system-level demonstrations and mature crosslayer tools. The full exploitation of these alternative technologies requires holistic approaches whereby the devices, circuits, and system-level architecture (such as the cache coherent transfer mechanism and the memory controller design) are developed hand-in-hand. This requires the development of integrated tool flows that enable rapid iteration at each level of the stack, and cross-layer optimization, e.g., the ability to quickly characterize the impact of component tradeoffs on system-level metrics. Moreover, demonstrations of these new technologies have been extremely limited in nature, largely limited to small, link-level demonstrations. Significant advances in fabrication, integration, packaging, testing, and validation must be made to enable more sophisticated system-level demonstrations of the technologies. To this end, one of the primary goals of this workshop is to bring together experts from various fields to identify the critical problems that need to be addressed, and a research agenda that, if successful, will make these promising technologies a commercial reality with a significant impact on the power performance efficiency of future systems.

To help address this need, the Workshop on Emerging Technologies for Interconnects will bring together key researchers, industry developers, and program managers in order to define an agenda for the research and commercial adoption of emerging interconnect technologies that hold the promise of much greater power-performance efficiency than conventional metal interconnects.

Expected Outcome

The expected outcome of this workshop is the identification of the critical research directions that need to be addressed to make emerging interconnect technologies a viable commercial alternative for chip-to-chip and on-chip interconnects. Key overall objectives are to advance broad, holistic approaches to the optimization of emerging technologies rather than piecemeal solutions, to catalyze the development of mature cross-layer toolsets, and to enable sophisticated prototypes that clearly demonstrate the power-performance benefits and commercial viability of these approaches.