Contact Information
Avinash Karanth Kodi
Professor   
Department of Electrical Engineering and Computer Science Russ College of Engineering and Technology Ohio University 322D Stocker Center Athens, OH 45701
Office: STKR 322D
Tel: (740)-597-1481
Fax: (740)-593-0007
E-mail: kodi [at] ohio [dot] edu
Resume: CV
Biography
I received my PhD and MS from Electrical and Computer Engineering Department from The University of Arizona in 
August 2006 and May 2003 respectively. I completed my BE in Electronics and Communications in February 2000
from Manipal Institute of Technology, Mangalore University. I was a post-doctoral scholar at the High-Performance
Computing Architectures and Technologies (HPCAT) Laboratory at The University of Arizona from 2006 to 2007.

Presently, I am a Professor at the School of Electrical Engineering and Computer Science at Ohio University and a
Senior Member of IEEE and a Member of ACM. I lead the Technologies for Emerging Computer
Architecture Laboratory (TEAL)
at Ohio University.

My research interests include computer architecture, optical interconnects, Network-on-Chips (NoCs) and emerging
technologies such as nanophotonics, 3D and wireless interconnects. I am the recipient of the NSF CAREER Award
in 2011, Best Paper Award at the ICCD 2013 conference and my papers have been nominated for Best Paper at
IEEE
Symposium on Network-on-Chips (NoCs) in May 2010 and IEEE Asia & South Pacific Design Automation
Conference (ASP-DAC) in January 2009. My 2004 Hot Interconnects paper was selected as one of the Top Picks
for IEEE MICRO magazine in 2005. I have been on the Program Committee of NoCs 2016, MPSoCs ('14, '15, '16),
ACM Nanocom '16, Hot Interconnects '10, external Program Committee for MICRO'12 and a co-Guest Editor for
IEEE Transactions on Emerging Topics for Computing ('15-'16) and Journal of Parallel and Distributed (JPDC) ('10-'11).
Honors & Awards
Teaching -
Research Interests
Selected Publications

Machine Learning Enabled Power-Aware Network-on-Chip Design [DATE'17]
Dynamic Error Mitigation in NoCs using Intelligent Prediction Techniques [MICRO'16]
QORE: A Fault-tolerant Network-on-Chip Architecture with Power-Efficient Quad Function Channel (QFC) Buffers [HPCA'14]
Runtime Adaptive Scrubbing for Fault-Tolerant Networks-on-Chips (NoCs) Architectures [ICCD'13, Best Paper]
Reconfiguration of 3D Photonic On-Chip Interconnects for Maximizing Performance and Improving Fault Tolerance [MICRO'12]
iWISE: Inter-Router Wireless Scalable Express Channels for Network-on-Chips (NoCs) Architecture [HotInt'11]

Last Updated August 9, 2017